JPH0557741B2 - - Google Patents

Info

Publication number
JPH0557741B2
JPH0557741B2 JP9082423A JP8242390A JPH0557741B2 JP H0557741 B2 JPH0557741 B2 JP H0557741B2 JP 9082423 A JP9082423 A JP 9082423A JP 8242390 A JP8242390 A JP 8242390A JP H0557741 B2 JPH0557741 B2 JP H0557741B2
Authority
JP
Japan
Prior art keywords
film
forming
deposited film
deposited
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9082423A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0348459A (ja
Inventor
Shuichi Kameyama
Kazuya Kikuchi
Hiroshi Shimomura
Mizuki Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of JPH0348459A publication Critical patent/JPH0348459A/ja
Publication of JPH0557741B2 publication Critical patent/JPH0557741B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
JP2082423A 1989-04-26 1990-03-29 半導体装置及びその製造方法 Granted JPH0348459A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10860989 1989-04-26
JP1-108609 1989-04-26

Publications (2)

Publication Number Publication Date
JPH0348459A JPH0348459A (ja) 1991-03-01
JPH0557741B2 true JPH0557741B2 (en]) 1993-08-24

Family

ID=14489140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2082423A Granted JPH0348459A (ja) 1989-04-26 1990-03-29 半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US5045493A (en])
EP (1) EP0399231B1 (en])
JP (1) JPH0348459A (en])
DE (1) DE69032074T2 (en])

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2842682B2 (ja) * 1990-11-08 1999-01-06 シャープ株式会社 半導体装置の製造方法
US5422290A (en) * 1994-02-28 1995-06-06 National Semiconductor Corporation Method of fabricating BiCMOS structures
JPH07335773A (ja) * 1994-06-10 1995-12-22 Hitachi Ltd 半導体集積回路装置の製造方法
US5594268A (en) * 1994-08-03 1997-01-14 National Semiconductor Corporation Method of manufacturing high performance bipolar transistors in a BICMOS process
JP2776350B2 (ja) * 1995-12-18 1998-07-16 日本電気株式会社 半導体集積回路装置の製造方法
US6245604B1 (en) * 1996-01-16 2001-06-12 Micron Technology Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
US6001701A (en) * 1997-06-09 1999-12-14 Lucent Technologies Inc. Process for making bipolar having graded or modulated collector
US6448124B1 (en) 1999-11-12 2002-09-10 International Business Machines Corporation Method for epitaxial bipolar BiCMOS
JP4951807B2 (ja) * 2000-07-11 2012-06-13 ソニー株式会社 半導体装置及びその製造方法
US7064416B2 (en) * 2001-11-16 2006-06-20 International Business Machines Corporation Semiconductor device and method having multiple subcollectors formed on a common wafer
US6867440B1 (en) * 2002-08-13 2005-03-15 Newport Fab, Llc Self-aligned bipolar transistor without spacers and method for fabricating same
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
KR100672682B1 (ko) * 2005-12-28 2007-01-24 동부일렉트로닉스 주식회사 바이폴라트랜지스터의 제조방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
US4929992A (en) * 1985-09-18 1990-05-29 Advanced Micro Devices, Inc. MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions
US4922318A (en) * 1985-09-18 1990-05-01 Advanced Micro Devices, Inc. Bipolar and MOS devices fabricated on same integrated circuit substrate
JPH0628296B2 (ja) * 1985-10-17 1994-04-13 日本電気株式会社 半導体装置の製造方法
GB2186117B (en) * 1986-01-30 1989-11-01 Sgs Microelettronica Spa Monolithically integrated semiconductor device containing bipolar junction,cmosand dmos transistors and low leakage diodes and a method for its fabrication
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
JPH0638472B2 (ja) * 1986-11-05 1994-05-18 日本電気株式会社 半導体装置の製造方法
DE3882251T2 (de) * 1987-01-30 1993-10-28 Texas Instruments Inc Verfahren zum Herstellen eines bipolaren Transistors unter Verwendung von CMOS-Techniken.
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process
JPS63296365A (ja) * 1987-05-28 1988-12-02 Matsushita Electronics Corp Ｂｉ−ＣＭＯＳ半導体装置の製造方法
JPH01282857A (ja) * 1988-05-10 1989-11-14 Seiko Epson Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US5045493A (en) 1991-09-03
DE69032074D1 (de) 1998-04-09
JPH0348459A (ja) 1991-03-01
EP0399231B1 (en) 1998-03-04
DE69032074T2 (de) 1998-10-01
EP0399231A3 (en) 1991-03-13
EP0399231A2 (en) 1990-11-28

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Legal Events

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LAPS Cancellation because of no payment of annual fees